Shared hardware accelerator architectures for heterogeneous MPSoCs
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6575424/6581516/06581549.pdf?arnumber=6581549
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. GMMSO: game model-combined improved moth search optimization approach for reconfigurable asymmetric multi-processor system-on-chip architecture;Engineering Optimization;2022-01-26
2. A high performance scalable fuzzy based modified Asymmetric Heterogene Multiprocessor System on Chip (AHt-MPSOC) reconfigurable architecture;Journal of Intelligent & Fuzzy Systems;2022-01-25
3. An Efficient Implementation of Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) Framework in FPGA-Based Multiprocessor System;Arabian Journal for Science and Engineering;2020-05-26
4. Generating Optimized Multicore Accelerator Architectures;2019 IX Brazilian Symposium on Computing Systems Engineering (SBESC);2019-11
5. Hardware resource utilization optimization in FPGA-based Heterogeneous MPSoC architectures;Microprocessors and Microsystems;2015-11
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