Significant Lifetime Improvement of Negative Bias Thermal Instability by Plasma Enhanced Atomic Layer Deposition SiN in Stress Memorization Technique
Author:
Affiliation:
1. State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China
Funder
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/66/10636181/10521911.pdf?arnumber=10521911
Reference24 articles.
1. Novel locally strained channel technique for high performance 55nm CMOS
2. Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application;Chen
3. Stress Memorization Technique (SMT) Optimization for 45nm CMOS
4. Mechanism of Stress Memorization Technique (SMT) and Method to Maximize Its Effect
5. Stress Modulation of PECVD Silicon Nitride
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