A Partially-redundant Flip-flip Suitable for Mitigating Single Event Upsets in a FD-SOI Process with Low Performance Overhead
Author:
Affiliation:
1. Kyoto Institute of Technology,Department of Electronics,Kyoto,Japan,606-8585
Funder
The University of Tokyo
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10529283/10529298/10529307.pdf?arnumber=10529307
Reference10 articles.
1. Technology downscaling worsening radiation effects in bulk: SOI to the rescue
2. A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI
3. Investigating of SER in 28 nm FDSOI-Planar and Comparing with SER in Bulk-FinFET
4. Utilizing device stacking for area efficient hardened SOI flip-flop designs
5. Optimization for SEU/SET Immunity on 0.15 $\mu$m Fully Depleted CMOS/SOI Digital Logic Devices
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