Extended MTJ TDDB Model, and Improved STT-MRAM Reliability With Reduced Circuit and Process Variabilities-Reference-Cited by-同舟云学术

Extended MTJ TDDB Model, and Improved STT-MRAM Reliability With Reduced Circuit and Process Variabilities

Published:2022-03 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Reliability Physics Symposium (IRPS)
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Author:

Naik V. B.¹,Lim J. H.¹,Yamane K.¹,Kwon J.¹,B. Behin-Aein¹,Chung N. L.¹,K S.¹,Hau L. Y.¹,Chao R.¹,Chiang C.¹,Huang Y.¹,Pu L.¹,Otani Y.¹,Jang S.H.¹,Balasankaran N.¹,Neo W. P.¹,Ling T.¹,Ting J. W.¹,Yoon H.¹,Mueller J.¹,Pfefferling B.¹,Kallensee O.¹,Merbeth T.¹,Seet C.S.¹,Wong J.¹,You Y. S.¹,Soss S.¹,Chan T. H.¹,Siah S. Y.¹

Affiliation:

1. Globalfoundries Singapore Pte. Ltd.,Singapore,738406

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9764406/9764408/09764563.pdf?arnumber=9764563

Reference11 articles.

1. JEDEC-Qualified Highly Reliable 22nm FD-SOI Embedded MRAM For Low-Power Industrial-Grade, and Extended Performance Towards Automotive-Grade-1 Applications

2. 2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications

3. A Reliable TDDB Lifetime Projection Model Verified Using 40Mb STT-MRAM Macro at Sub-ppm Failure Rate To Realize Unlimited Endurance for Cache Applications

4. A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process

5. Impact of self-heating on reliability predictions in STT-MRAM

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1. Embedded STT-MRAM for Automotive Applications;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03

2. Smart Hammering: A practical method of pinhole detection in MRAM memories;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04

3. Full reliability characterization of three-terminal SOT-MTJ devices and corresponding arrays;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03