Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging
Author:
Affiliation:
1. Kobe University,Graduate School of Science, Technology, and Innovation,Hyogo,Japan
2. e-SYNC Co., Ltd,Kyoto,Japan
3. MegaChips Corp,Osaka,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9764406/9764408/09764457.pdf?arnumber=9764457
Reference15 articles.
1. IEC 61000-6-2: Electromagnetic compatibility (EMC) - Part 6-2: Generic standards - Immunity for industrial environments,2016
2. Towards Sound Approaches to Counteract Power-Analysis Attacks
3. Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices
4. A dual-mode successive approximation register analog to digital converter to detect malicious off-chip power noise measurement attacks
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1. Chip-Backside Vulnerability to Intentional Electromagnetic Interference in Integrated Circuits;IEEE Transactions on Electromagnetic Compatibility;2024
2. Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging;IEICE Transactions on Electronics;2023-10-01
3. A better practice for Body Biasing Injection;2023 Workshop on Fault Detection and Tolerance in Cryptography (FDTC);2023-09-10
4. Characterization of Backside ESD Impacts on Integrated Circuits;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03
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