A Fully Synthesizable All-Digital Phase-Locked Loop with Parametrized and Portable Architecture-Reference-Cited by-同舟云学术

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A Fully Synthesizable All-Digital Phase-Locked Loop with Parametrized and Portable Architecture

Published:2021-01-26 Issue: Volume: Page:
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Container-title:2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)
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Author:

Khalirbaginov Rustam

Funder

Foundation for Assistance to Small Innovative Enterprises

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9396056/9396068/09396574.pdf?arnumber=9396574

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of high-resolution and wide-range time-to-digital converter;Eighth International Conference on Electronic Technology and Information Science (ICETIS 2023);2023-06-20

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