From visual to logical formalisms for SoC validation
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/6950639/6961832/06961855.pdf?arnumber=6961855
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. ARISTOTLE: Feature Engineering for Scalable Application-Level Post-Silicon Debugging;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-09
2. Demystifying Attestation in Intel Trust Domain Extensions via Formal Verification;IEEE Access;2021
3. Online Firmware Functional Validation Scheme Using Colored Petri Net Model;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-07
4. Formal Foundations for Intel SGX Data Center Attestation Primitives;Formal Methods and Software Engineering;2020
5. Application level hardware tracing for scaling post-silicon debug;Proceedings of the 55th Annual Design Automation Conference;2018-06-24
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