On the Detectability of Scan Chain Internal Faults An Industrial Case Study

Author:

Yang Fan,Chakravarty Sreejit,Devta-Prasanna Narendra,Reddy Sudhakar M,Pomeranz Irith

Publisher

IEEE

Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Conventional Tests for Approximate Scan Logic;IEEE Design & Test;2024-06

2. Near-Threshold-at-Gate based Test for Stuck-on Fault in Scan-chain Testing;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

3. Test Generation for Defect-Based Faults of Scan Flip-Flops;2023 IEEE 41st VLSI Test Symposium (VTS);2023-04-24

4. Usable Circuits with Imperfect Scan Logic;2022 IEEE 31st Asian Test Symposium (ATS);2022-11

5. Test Sequences for Faults in the Scan Logic;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-10

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