Author:
Wang Xiaoxiao,Guo Yueyu,Ramhan Tauhid,Zhang Dongrong,Tehranipoor Mark
Cited by
8 articles.
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1. Design-for-Testability and Its Impact on Logic Locking;Understanding Logic Locking;2023-09-23
2. Infrastructure Supporting Logic Locking;Understanding Logic Locking;2023-09-23
3. A Novel Dual Logic Locking Method to Prevent Counterfeit IP/IC;2022 IEEE International Test Conference in Asia (ITC-Asia);2022-08
4. TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-12
5. System-Level Counterfeit Detection Using On-Chip Ring Oscillator Array;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-12