Author:
Trabelsi Ltci Oualid,Sauvage Ltci Laurent,Danger Ltci Jean-Luc
Cited by
2 articles.
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1. Modeling Clock Glitch Fault Injection Effects on a RISC-V Microcontroller;2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS);2024-07-03
2. Fault Model Analysis of DRAM under Electromagnetic Fault Injection Attack;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04