Accelerating chip design with machine learning: From pre-silicon to post-silicon-Reference-Cited by-同舟云学术

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Accelerating chip design with machine learning: From pre-silicon to post-silicon

Published:2017-09 Issue: Volume: Page:
ISSN:
Container-title:2017 30th IEEE International System-on-Chip Conference (SOCC)
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Author:

Zhuo Cheng,Yu Bei,Gao Di

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8170502/8225969/08226046.pdf?arnumber=8226046

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Synthetic Benchmark for Data-Driven Pre-Si Analogue Circuit Verification;Electronics;2024-07-02

2. Experts in the Loop: Conditional Variable Selection Based on Deep Learning for Accelerating Post-Silicon Validation;IEEE Transactions on Semiconductor Manufacturing;2024-05

3. AI/ML algorithms and applications in VLSI design and technology;Integration;2023-11

4. Adaptive Planning Search Algorithm for Analog Circuit Verification;2023 International Semiconductor Conference (CAS);2023-10-11

5. Towards Machine Learning-Based FPGA Backend Flow: Challenges and Opportunities;Electronics;2023-02-13

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