Design and Modeling of Quad Gate-Stacked Nano Sheets Finfet Device and Its Implementation in Digital Applications
Author:
Affiliation:
1. The NorthCap University,Department of Multidisciplinary Engineering,Gurugram,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10579950/10580998/10581075.pdf?arnumber=10581075
Reference21 articles.
1. A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
2. Options beyond FinFETs at 5nm node;Thean,2016
3. Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node
4. Design and Optimization of Novel Shaped FinFET
5. Anisotropy of electron mobility in arbitrarily oriented FinFETs
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