Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization

Author:

Murray Kevin E.,Betz Vaughn

Publisher

IEEE

Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. TSTL-GNN: Graph-Based Two-Stage Transfer Learning for Timing Engineering Change Order Analysis Acceleration;Electronics;2024-07-23

2. Performance (Timing) Analysis;FPGA EDA;2024

3. Accelerating Static Timing Analysis Using CPU–GPU Heterogeneous Parallelism;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-12

4. Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs;2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2023-06-20

5. CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper);2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP);2021-07

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