3D-Stacked 2T0C-DRAM Cells Using Al2O3/TiO2-Based 2DEG FETs
Author:
Affiliation:
1. School of Microelectronics, Fudan University, Shanghai, China
2. School of Integrated Circuit, Southeast University, Nanjing, Jiangsu, China
Funder
National Natural Science Foundation of China
Support Plans for the Youth Top-Notch Talents of China
Major Projects of Zhangjiang National Innovation District
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/55/10577506/10539982.pdf?arnumber=10539982
Reference18 articles.
1. Capacitor-less dynamic random access memory based on a III–V transistor with a gate length of 14 nm
2. Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM
3. Double-Gate W-Doped Amorphous Indium Oxide Transistors for Monolithic 3D Capacitorless Gain Cell eDRAM
4. First Demonstration of Stacked 2T0C-DRAM Bit-Cell Constructed by Two-Layers of Vertical Channel-All-Around IGZO FETs Realizing 4F2 Area Cost
5. 3D Monolithically Integrated Device of Si CMOS Logic, IGZO DRAM-like, and 2D MoS2 Phototransistor for Smart Image Sensing
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