Inner Product Accelerating Scheme Based on RRAM Array for Attention-Mechanism Neural Network-Reference-Cited by-同舟云学术

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Inner Product Accelerating Scheme Based on RRAM Array for Attention-Mechanism Neural Network

Published:2024-03 Issue:3 Volume:45 Page:360-363
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Chen Yiyang¹^ORCID,Han Lixia¹^ORCID,Zhang Yizhou¹^ORCID,Zhou Zheng¹^ORCID,Huang Peng¹^ORCID,Li Can²^ORCID,Liu Lifeng¹^ORCID,Kang Jinfeng¹^ORCID

Affiliation:

1. School of Integrated Circuits, Peking University, Beijing, China

2. Department of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, SAR, China

Funder

National Key Research and Development Program

National Natural Science Foundation of China Program

111 Project Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/55/10449685/10387454.pdf?arnumber=10387454

Reference17 articles.

1. Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memory

2. Gradient descent-based programming of analog in-memory computing cores

3. Monolithic 3D Integration of High Endurance Multi-Bit Ferroelectric FET for Accelerating Compute-In-Memory

4. Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects

5. Forming-free and Annealing-free V/VO_x/HfWO_x/Pt Device Exhibiting Reconfigurable Threshold and Resistive switching with high speed (<30ns) and high endurance (>10¹²/>10¹⁰)

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