Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications
Author:
Affiliation:
1. Air Force Engineering University,Air and Missile Defense College,Xi’an,China
2. National University of Defense Technology,School of Computer,Changsha,China
3. Unit 66029 of PLA, Xilin Gol League,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10424971/10426625/10426736.pdf?arnumber=10426736
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1. 6.5 A 400Gb/s Transceiver for PAM-4 Optical Direct-Detect Application in 16nm FinFET
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3. A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS
4. A second-order semidigital clock recovery circuit based on injection locking
5. A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding
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