Novel Three-Input Gates for Silicon Quantum Dot
Author:
Funder
CAPES
CNPq
FAPEMIG
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9529954/9529346/09530002.pdf?arnumber=9530002
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3. Simulating Charged Defects in Silicon Dangling Bond Logic Systems to Evaluate Logic Robustness;IEEE Transactions on Nanotechnology;2024
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