Reduced-Order Generalized Integrator-Based Phase-Locked Loop: Performance Improvement for Grid Synchronization of Single-Phase Inverters-Reference-Cited by-同舟云学术

Reduced-Order Generalized Integrator-Based Phase-Locked Loop: Performance Improvement for Grid Synchronization of Single-Phase Inverters

Author:

Bamigbade Abdullahi¹^ORCID,Umesh B. S.²^ORCID,Khadkikar Vinod²^ORCID,Moursi Mohamed Shawky El²^ORCID,Zeineldin H. H.³^ORCID,Hosani Mohamed Al⁴^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, New York University, Brooklyn, NY, USA

2. Advanced Power and Energy Center (APEC), Electrical Engineering and Computer Science Department, Khalifa University, Abu Dhabi, UAE

3. APEC, Khalifa University, Abu Dhabi, UAE

4. Department of Demand Side Management, Abu Dhabi Distribution Company, Abu Dhabi, UAE

Funder

Khalifa University of Science, Technology and Research

ASPIRE

ASPIRE Virtual Research Institute

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Energy Engineering and Power Technology

Link

Reference43 articles.

4. Design of a high-performance high-pass generalized integrator based single-phase PLL;kulkarni;J Power Electron,2017

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