Design and Implementation of Low Power and High- Speed Full Adder-Reference-Cited by-同舟云学术

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Design and Implementation of Low Power and High- Speed Full Adder

Published:2021-08-27 Issue: Volume: Page:
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Container-title:2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)
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Author:

Yadhav M Arunkumar,Deepa

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9573500/9573517/09574023.pdf?arnumber=9574023

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A comprehensive analysis of ultra low power GNRFET based 20T hybrid full adder for computing applications;Physica Scripta;2024-07-05

2. Design and Implementation of Low Power-Novel Encoder Based Flash ADC;2023 International Conference on Smart Systems for applications in Electrical Sciences (ICSSES);2023-07-07

3. Design of DADDA Multiplier Using High Performance and Low Power Full Adder;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06

4. Design of Wallace tree multiplier circuit using high performance and low power full adder;E3S Web of Conferences;2023

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