An ADC Input Buffer with Optimized Linearity
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8540788/8564801/08564827.pdf?arnumber=8564827
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An 8-GHz Bandwidth Push-Pull Input Buffer Based on Cascode Source Follower;2023 5th International Conference on Circuits and Systems (ICCS);2023-10-27
2. A Wideband ADC Input Buffer Based on AC-Coupled Super Source Follower;2023 International Conference on Microwave and Millimeter Wave Technology (ICMMT);2023-05-14
3. A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower;2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2022-10-28
4. A Self-Regulating Negative Charge Pump Using Multi-Phase Clock for Wideband ADCs;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
5. A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS;IEICE Electronics Express;2021-06-10
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