Author:
Eyerman Stijn,Eeckhout Lieven
Funder
Research Foundation — Flanders (FWO)
European Research Council under the European Community's Seventh Framework Programme
ERC
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Hardware and Architecture
Cited by
25 articles.
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1. Cache Line Pinning for Mitigating Row Hammer Attack;Proceedings of the 53rd International Conference on Parallel Processing;2024-08-12
2. Divide&Content: A Fair OS-Level Resource Manager for Contention Balancing on NUMA Multicores;IEEE Transactions on Parallel and Distributed Systems;2023-11
3. WinDRAM: Weak rows as in‐DRAM cache;Concurrency and Computation: Practice and Experience;2022-09-26
4. An Investigation & Analysis of Interference in Multicore Enviorment;2022 IEEE 11th International Conference on Communication Systems and Network Technologies (CSNT);2022-04-23
5. Hy-Sched: A Simple Hyperthreading-Aware Thread to Core Allocation Strategy;IEEE Computer Architecture Letters;2021-01-01