Analysis of Block Level PnR Flow to Increase the Cell Density in Less Congested Regions

Author:

Dargar Shashi Kant1,Nagineni Venkatesh1,Reddy Telukuntla Surendra1,Subbaramaiah Talapala1,Gupta Amit2,Sainath Reddy Ranganna Gari1

Affiliation:

1. Kalasalingam Academy of Research and Education,Department of ECE,Tamilnadu,India

2. Nalla Malla Reddy Engineering College,Department of ECE,Telangana,India

Publisher

IEEE

Reference15 articles.

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4. Choosing appropriate utilization factor and metal layer numbers for an efficient floor plan in vlsi physical design;gunnala;International Journal of Applied Engineering Research IJAER,2012

5. Physical Design Implementation of a complex IP core aimed at area optimization;karekar;IRJET,2016

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Implement a PnR Flow to Boost the Pin Density in Block Level Chip Design;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28

2. Design of PnR Flow For Block Level Chip for Optimizing Leakage Power;2024 Third International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS);2024-03-14

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