Design and Analysis of CMOS Low-Phase-Noise Low-Jitter Subharmonically Injection-Locked VCO With FLL Self-Alignment Technique-Reference-Cited by-同舟云学术

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Design and Analysis of CMOS Low-Phase-Noise Low-Jitter Subharmonically Injection-Locked VCO With FLL Self-Alignment Technique

Published:2016-12 Issue:12 Volume:64 Page:4632-4645
ISSN:0018-9480
Container-title:IEEE Transactions on Microwave Theory and Techniques
language:
Short-container-title:IEEE Trans. Microwave Theory Techn.

Author:

Chang Hong-Yeh,Chan Chun-Ching,Shen Ian Yi-En,Yeh Yen-Liang,Huang Shu-Yan

Funder

Ministry of Science and Technology (MOST), Taiwan

Chip Implementation Center, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Radiation

Link

http://xplorestaging.ieee.org/ielx7/22/7776993/07748445.pdf?arnumber=7748445

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Analysis of a V-band CMOS Sextuple SILVCO using Transformer and Cascade-series Coupling with a Frequency-tracking Loop;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2023

2. Injection-Locking Techniques for CMOS Millimeter-Wave and Terahertz Signal Generation;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-07

3. A 30-36.6 GHz Low Jitter Degradation SIL QVCO with Frequency-tracking Loop in 65 nm CMOS for 5G Frontend Applications;EUR MICROW INTEGRAT;2021

4. CMOS analog and mixed-signal phase-locked loops: An overview;Journal of Semiconductors;2020-11-01

5. A V-Band CMOS Low-DC-Power Wide-Locking-Range Divide-by-6 Injection-Locked Frequency Divider Using Transformer Coupling;IEEE Microwave and Wireless Components Letters;2020-06

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