A 6-bit Segmented DAC Architecture With up to 56-GHz Sampling Clock and 6-VppDifferential Swing-Reference-Cited by-同舟云学术

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A 6-bit Segmented DAC Architecture With up to 56-GHz Sampling Clock and 6-VppDifferential Swing

Published:2016 Issue: Volume: Page:1-11
ISSN:0018-9480
Container-title:IEEE Transactions on Microwave Theory and Techniques
language:
Short-container-title:IEEE Trans. Microwave Theory Techn.

Author:

Balteanu Andreea,Schvan Peter,Voinigescu Sorin P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Radiation

Link

http://xplorestaging.ieee.org/ielx7/22/7425309/7416003.pdf?arnumber=7416003

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 6-bit 56-GSa/s DAC in 55 nm SiGe BiCMOS;2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS);2021-12-05

2. Challenges in silicon photonics modulators for data center interconnect applications;Optics & Laser Technology;2021-12

3. Silicon modulator design using a system-oriented methodology for high-speed data center interconnect PAM-4 applications;Optics Communications;2021-08

4. A 64 GBaud 6-Bit Current Steering DAC With a Binary Tree Current Summing Network;2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2020-11-23

5. 32-GS/s 6-bit DAC based on SiGe technology for IM-DD OFDM systems with non-uniform quantization;Optics Express;2019-03-06

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