Modeling of Metal-Fill Parasitic Capacitance and Application to On-Chip Slow-Wave Structures-Reference-Cited by-同舟云学术

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Modeling of Metal-Fill Parasitic Capacitance and Application to On-Chip Slow-Wave Structures

Published:2017-05 Issue:5 Volume:65 Page:1456-1464
ISSN:0018-9480
Container-title:IEEE Transactions on Microwave Theory and Techniques
language:
Short-container-title:IEEE Trans. Microwave Theory Techn.

Author:

Shilimkar Vikas S.^ORCID,Weisshaar Andreas

Funder

Center for Design of Analog and Digital Integrated Circuits

student fellowship from ARFTG

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Radiation

Link

http://xplorestaging.ieee.org/ielx7/22/7919344/07829342.pdf?arnumber=7829342

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel 3-D Printed Dual-Port Rectenna for Simultaneous Energy Harvesting and Backscattering of a Passively Generated UWB Pulse;IEEE Transactions on Microwave Theory and Techniques;2024-01

2. A Compact and Broadband On-Chip Delay Line Design Based on the Bridged T-Coil;2021 IEEE 25th Workshop on Signal and Power Integrity (SPI);2021-05-10

3. Timing-Aware Fill Insertions with Design-Rule and Density Constraints;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021

4. Timing-Aware Fill Insertions with Design-Rule and Density Constraints;2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD);2019-11

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