A Three-Step Multi-Resolution Time-to-Digital Converter-Reference-Cited by-同舟云学术

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A Three-Step Multi-Resolution Time-to-Digital Converter

Published:2023-05-21 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Zhuang Yan¹,Yan Jiang¹,Zhang Jing¹,Wang Yu²,Qiao Fei²,Zhang Jiangwei²,Wei Qi³,Zhu Qingpeng⁴,Sun Wenxiu⁴,Shi Ge⁵

Affiliation:

1. School of Information, North China University of Technology,Beijing,China

2. Tsinghua University,Department of Electronic Engineering,Beijing,China

3. Tsinghua University,Department of Precision Instrument,Beijing,China

4. SenseTime Research and Tetras.AI,Shenzhen,China

5. College of Mechanical and Electrical Engineering, China Jiliang University,Hangzhou,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181803.pdf?arnumber=10181803

Reference8 articles.

1. A 10ps 500MHz time-to-digital converter in 0.18μm CMOS technology for ADC

2. A high resolution time-to-digital converter using two-level vernier delay line technique

3. A 14-b, 850fs fully synthe- sizable stochastic-based branching time-to-digital converter in 65nm CMOS[C];teh;2018 IEEE International Symposium on Circuits and Systems (ISCAS),2018

4. Two-Dimensions Vernier Time-to-Digital Converter

5. A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification

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