Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies-Reference-Cited by-同舟云学术

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Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies

Published:2023-05-21 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Wu Zhengfeng¹,Savidis Ioannis¹

Affiliation:

1. Drexel University,Department of Electrical and Computer Engineering,Philadelphia,PA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181617.pdf?arnumber=10181617

Reference24 articles.

1. Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks

2. High-performance CMOS variability in the 65-nm regime and beyond

3. GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits

4. A Comparison of Three Methods for Selecting Values of Input Variables in the Analysis of Output from a Computer Code

5. Deeper Insights Into Graph Convolutional Networks for Semi-Supervised Learning

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Comparative Analysis of Graph Isomorphism and Graph Neural Networks for Analog Hierarchy Labeling;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

2. Hybrid Utilization of Subgraph Isomorphism and Relational Graph Convolutional Networks for Analog Functional Grouping Annotation;2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD);2023-09-10

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