Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology
Author:
Affiliation:
1. University of Twente,Radio Systems Group,The Netherlands
2. University of Twente,Integrated Circuit Design Group,The Netherlands
Funder
Analog Approximate Accelerators
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181651.pdf?arnumber=10181651
Reference12 articles.
1. A novel hybrid pass logic with static CMOS output drive full-adder cell;zhang;2003 IEEE International Symposium on Circuits and Systems (ISCAS),2003
2. Low-power logic styles: CMOS versus pass-transistor logic
3. Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
4. An ultra low-voltage standard cell library in 65-nm CMOS process technology
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