Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle
Author:
Affiliation:
1. National Sun Yat-Sen University,Dept. of Electrical Engineering,Kaohsiung,Taiwan,80424
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181491.pdf?arnumber=10181491
Reference7 articles.
1. Dynamic power reduction through clock gating technique for low power memory applications
2. Single-chip dc-dc buck converter design based on PWM with high-efficiency in light load;wang;International Journal of Electronics Letters,2022
3. Low Power Digital PWM Buck Converter With a Clock-Gating Shift-Register
4. A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS
5. A Novel High Resolution DPWM Circuit for High Frequency Digitally Controlled DC-DC Converter
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