LOCS: LOw-Latency and ConStant-Timing Implementation of Fixed-Weight Sampler for HQC
Author:
Affiliation:
1. Villanova University,Department of Electrical and Computer Engineering,Villanova,PA,USA,19087
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181319.pdf?arnumber=10181319
Reference18 articles.
1. Lightweight hardware implementation of binary ring-lwe pqc accelerator;lucas;IEEE Computer Architecture Letters,2022
2. Fpga implementation of compact hardware accelerators for ring-binary-lwe based post-quantum cryptography;he;ACM Transactions on Reconfigurable Technology and Systems,2022
3. Towards a fast and efficient hardware implementation of HQC;deshpande;Cryptology ePrint Archive,2022
4. An Efficient and Parallel R-LWE Cryptoprocessor
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A High Efficiency Hardware Design for the Post-Quantum KEM HQC;2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST);2024-05-06
2. Hardware Circuits and Systems Design for Post-Quantum Cryptography—A Tutorial Brief;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-03
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