Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited)-Reference-Cited by-同舟云学术

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited)

Published:2023-05-21 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Tsai Hsinyu¹,Narayanan Pritish¹,Jain Shubham²,Ambrogio Stefano¹,Hosokawa Kohji³,Ishii Masatoshi³,Mackin Charles¹,Chen Ching-Tzu²,Okazaki Atsuya³,Nomura Akiyo³,Boybat Irem⁴,Muralidhar Ramachandran²,Frank Martin M.²,Yasuda Takeo³,Friz Alexander¹,Kohda Yasuteru³,Chen An¹,Fasoli Andrea¹,Rasch Malte J.²,Woźniak Stanisław⁴,Luquin Jose¹,Narayanan Vijay²,Burr Geoffrey W.¹

Affiliation:

1. IBM Research–Almaden,San Jose,CA,USA

2. IBM Research-T. J. Watson Research Center,Yorktown Heights,NY,USA

3. IBM Tokyo Research Laboratory,Tokyo,Japan

4. IBM Research,Zurich, Rüschlikon,Switzerland

Funder

IBM Research AI Hardware Center

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181650.pdf?arnumber=10181650

Reference18 articles.

1. Fully on-chip MAC at 14nm enabled by accurate row-wise programming of PCM-based weights and parallel vector-transport in duration-format;narayanan;Symposium on VLSI Technology,2021

2. Equivalent-accuracy accelerated neural-network training using analogue memory;ambrogio;Nature,2018

3. Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory

4. HERMES Core – A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing

5. Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element

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1. A CMOS Analog Neuron Circuit with A Multi-Level Memory;2023 International Conference on Microelectronics (ICM);2023-12-17