Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect

Author:

Shrestha Pratik1,Savidis Ioannis1

Affiliation:

1. Drexel University,Department of Electrical and Computer Engineering,Philadelphia,Pennslyvania,19104

Publisher

IEEE

Reference15 articles.

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5. IWLS 2005 benchmarks;albrecht;Int Workshop Logic Synthesis,2005

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