A temperature and process compensation circuit for resistive-based in-memory computing arrays
Author:
Affiliation:
1. Aalto University School of Electrical Engineering,Department of Electronics and Nanoengineering,Espoo,Finland
Funder
Academy of Finland projects EHIR
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181619.pdf?arnumber=10181619
Reference14 articles.
1. Analog In-memory Computing in FeFET-based 1TIR Array for Edge AI Applications;saito;2021 Symposium on VLSI Circuits,2021
2. Hardware Neural Network using Hybrid Synapses via Transfer Learning: WOx Nano-Resistors and TiOx RRAM Synapse for Energy-Efficient Edge-AI Sensor
3. Ultra low power beta multiplier-based current reference circuit
4. ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory
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1. On-chip Built-In Self-Calibration of Thermal Variations for Mixed-Signal In-Memory Computing;2024 IEEE European Test Symposium (ETS);2024-05-20
2. Neurons With Captive Synaptic Devices for Temperature Robust Spiking Neural Networks;IEEE Electron Device Letters;2024-03
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