A 61 mHz - 3.4 Hz High-pass Capacitively Coupled Analog Frontend with Tunnelling Biasing and Output DC Servo Loop
Author:
Affiliation:
1. School of Integrated Circuit Science and Engineering, Beihang University,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181654.pdf?arnumber=10181654
Reference13 articles.
1. A 2- 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop
2. An 80-mVpp Linear-Input Range, 1.6-GΩ Input Impedance, Low-Power Chopper Amplifier for Closed-Loop Neural Recording That Is Tolerant to 650-mVpp Common-Mode Interference
3. Design of an Extreme Low Cutoff Frequency Highpass Frontend for CMOS ISFET via Direct Tunneling Principle
4. Analysis of switched-capacitor common-mode feedback circuit
5. A 1V 3.5 μW Bio-AFE With Chopper-Capacitor-Chopper Integrator-Based DSL and Low Power GM-C Filter
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