eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric Sparse Matrix-Vector Multiplication
Author:
Affiliation:
1. Fudan University,State Key Lab of ASIC & System,Shanghai,China
2. Gallatin School of Individualized Study, New York University,New York,USA
Funder
National Key Research and Development Program of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181734.pdf?arnumber=10181734
Reference31 articles.
1. A Survey of Indexing Techniques for Sparse Matrices
2. Conflict-free symmet-ric sparse matrix-vector multiplication on multicore architec-tures;elafrou;Proceedings of the International Conference for High Performance Computing Networking Storage and Analysis (SC),0
3. Scaling up HBM Efficiency of Top-K SpMV for Approximate Embedding Similarity on FPGAs
4. ILUS: An incomplete LU preconditioner in sparse skyline format
5. Communication latency aware low power NoC synthesis
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