Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC

Author:

Querbach Bruce,Khanna Rahul,Puligundla Sudeep,Blankenbeckler David,Chiang Patrick Yin,Crop Joseph

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-12

2. Run Time Memory Error Recovery Process in Networking System;2023 7th International Conference on System Reliability and Safety (ICSRS);2023-11-22

3. RFLSR based Productive MBIST Architecutre for VLSI;2022 Second International Conference on Advanced Technologies in Intelligent Control, Environment, Computing & Communication Engineering (ICATIECE);2022-12-16

4. An Efficient Stress Pattern Based on VMRQ-PRBS for DDR Training;IEEE Transactions on Electromagnetic Compatibility;2022-12

5. An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process;IEEE Access;2021

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