Optimized Design of Three-Level APF Voltage Loop Considering DC-Link Voltage Oscillations-Reference-Cited by-同舟云学术

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Optimized Design of Three-Level APF Voltage Loop Considering DC-Link Voltage Oscillations

Published:2024-05-17 Issue: Volume: Page:1391-1395
ISSN:
Container-title:2024 IEEE 10th International Power Electronics and Motion Control Conference (IPEMC2024-ECCE Asia)
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Author:

Yan Qingzeng¹,Guo Longzhen¹,Zhang Zixu¹,Xing Chengjian¹,He Jinkui¹

Affiliation:

1. China University of Petroleum (East China),College of New Energy,Qingdao,China,266580

Funder

National Natural Science Foundation of China

Fundamental Research Funds for the Central Universities

Natural Science Foundation of Shandong Province

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10567049/10567050/10567062.pdf?arnumber=10567062

Reference12 articles.

1. Wideband Series Harmonic Voltage Compensator for Enhancing Stability of Microgrids

2. LTP Modeling and Analysis of Frequency Coupling in PLL-Synchronized Converters for Harmonic Power Flow Studies

3. Investigation and mitigation of harmonic amplification problems caused by single-tuned filters

4. Online Inductance Identification and FPGA-Based Real-Time Digital Control Design for APF

5. A Robust DC-Link Voltage Control Strategy to Enhance the Performance of Shunt Active Power Filters Without Harmonic Detection Schemes

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