A radix-8 CMOS S/390 multiplier

Author:

Schwarz E.M.,Averill R.M.,Sigal L.J.

Publisher

IEEE Comput. Soc

Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Performance Comparison Review of Multiplier Designs;2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON);2022-12-02

2. Hardware Implementation of 64-Bits Data by Radix-8 FFT/IFFT for High Speed Applications;2022 8th International Conference on Signal Processing and Communication (ICSC);2022-12-01

3. Energy efficient signed and unsigned radix 16 booth multiplier design;Computers & Electrical Engineering;2021-03

4. A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-02

5. Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction;IEEE Transactions on Circuits and Systems I: Regular Papers;2017-02

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