Practical Verification of Railway Signalling Programs

Author:

Iliasov Alexei1,Taylor Dominic2ORCID,Laibinis Linas3ORCID,Romanovsky Alexander1ORCID

Affiliation:

1. Formal Route Limited, London, U.K.

2. Systra Scott Lister, London, U.K.

3. Institute of Computer Science, Vilnius University, Vilnius, Lithuania

Funder

EPSRC/UK STRATA

TRAMS-2 platform

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Formal Verification Method of CTCS-2 Level Train Control Engineering Data Based on the Reduced Ordered Binary Decision Diagram;IEEE Access;2024

2. LightF3: A Lightweight Fully-Process Formal Framework for Automated Verifying Railway Interlocking Systems;Proceedings of the 31st ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering;2023-11-30

3. Wireless Train Detection Based on Null-Filled UHF RFID Reader Antenna for Communications-Based Train Control;IEEE Transactions on Vehicular Technology;2023

4. The SafeCap Trajectory: Industry-Driven Improvement of an Interlocking Verification Tool;Reliability, Safety, and Security of Railway Systems. Modelling, Analysis, Verification, and Certification;2023

5. Verification and Validation for a Project Information Model Based on a Blockchain;Proceedings of Seventh International Congress on Information and Communication Technology;2022-07-27

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