A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits

Author:

Thonnart Yvain,Beigne Edith,Vivet Pascal

Publisher

IEEE

Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V;2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2023-08-28

2. Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design;2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2022-08-22

3. Automatic Timing Closure for Relative Timed Designs;2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC);2020-10-05

4. Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools;2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2019-05

5. NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization;IEEE Transactions on Circuits and Systems I: Regular Papers;2018-06

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