A portable and fault-tolerant microprocessor based on the SPARC v8 architecture

Author:

Gaisler J.

Publisher

IEEE Comput. Soc

Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An ARM-FPGA Hybrid Acceleration and Fault Tolerant Technique for Phase Factor Calculation in Spaceborne Synthetic Aperture Radar Imaging;IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing;2024

2. Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03

3. Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core Systems;Quality Control - An Anthology of Cases;2023-01-18

4. A European Roadmap to Leverage RISC-V in Space Applications;2022 IEEE Aerospace Conference (AERO);2022-03-05

5. DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA;Electronics;2021-12-30

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