Complex clock gating with integrated clock gating logic cell-Reference-Cited by-同舟云学术

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Complex clock gating with integrated clock gating logic cell

Published:2007 Issue: Volume: Page:
ISSN:
Container-title:2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era
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Author:

Bhutada Rani,Manoli Yiannos

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4446723/4449471/04449512.pdf?arnumber=4449512

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Power-aware scheduling of data-flow hardware circuits with symbolic control;Archives of Control Sciences;2023-07-26

2. Optimization of Cloning in Clock Gating Cells for High-Performance Clock Networks;Cognitive Informatics and Soft Computing;2022

3. ASIC Implementation and Optimization of 16 Bit SDRAM Memory Controller;2020 IEEE International Conference on Semiconductor Electronics (ICSE);2020-07

4. Exercising Symbolic Discrete Control for Designing Low-power Hardware Circuits: an Application to Clock-gating;IFAC-PapersOnLine;2018

5. Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-05

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