Checkpoint processing and recovery: towards scalable large instruction window processors

Author:

Akkary H.,Rajwar R.,Srinivasan S.T.

Publisher

IEEE Comput. Soc

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Speculative Register Reclamation;2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2023-02

2. Adaptable Register File Organization for Vector Processors;2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2022-04

3. The Forward Slice Core: A High-Performance, Yet Low-Complexity Microarchitecture;ACM Transactions on Architecture and Code Optimization;2022-01-31

4. Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme;Proceedings of the 26th Asia and South Pacific Design Automation Conference;2021-01-18

5. Relaxed Reorder Buffer Commit with Batch Context Switch;Proceedings of the International Conference on Computing Advancements;2020-01-10

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