Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4408231/4408232/04408251.pdf?arnumber=4408251
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3. High-Performance and Power-Saving Mechanism for Page Activations Based on Full Independent DRAM Sub-Arrays in Multi-Core Systems;IEEE Access;2023
4. Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly;Proceedings of the 2022 International Symposium on Memory Systems;2022-10-03
5. A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices;Proceedings of the 2022 International Symposium on Memory Systems;2022-10-03
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