Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4408231/4408232/04408251.pdf?arnumber=4408251
Cited by 83 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-09
2. High-Performance and Power-Saving Mechanism for Page Activations Based on Full Independent DRAM Sub-Arrays in Multi-Core Systems;IEEE Access;2023
3. Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly;Proceedings of the 2022 International Symposium on Memory Systems;2022-10-03
4. A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices;Proceedings of the 2022 International Symposium on Memory Systems;2022-10-03
5. HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips;2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO);2022-10
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