Author:
Sardashti Somayeh,Seznec Andre,Wood David A.
Cited by
45 articles.
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1. Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction Mechanism;Electronics;2024-03-23
2. Enterprise-Class Cache Compression Design;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02
3. Baryon: Efficient Hybrid Memory Management with Compression and Sub-Blocking;2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2023-02
4. SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches;2022 IEEE 40th International Conference on Computer Design (ICCD);2022-10
5. Exploring the Impacts of Software Cache Configuration for In-line Compressed Arrays;2022 IEEE High Performance Extreme Computing Conference (HPEC);2022-09-19