Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory-Reference-Cited by-同舟云学术

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Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory

Published:2011-10 Issue: Volume: Page:
ISSN:
Container-title:2011 International Conference on Parallel Architectures and Compilation Techniques
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Author:

Armejach Adria,Seyedi Azam,Titos-Gil Ruben,Hur Ibrahim,Cristal Adri´n,Unsal Osman S.,Valero Mateo

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6112806/6113772/06113844.pdf?arnumber=6113844

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. System-Scenario Methodology to Design a Highly Reliable Radiation-Hardened Memory for Space Applications;Computer Memory and Data Storage;2024-01-10

2. Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements;IEEE Access;2022

3. Hardware Approaches to Transactional Memory in Chip Multiprocessors;Handbook on Data Centers;2015

4. Flexicache: Highly Reliable and Low Power Cache under Supply Voltage Scaling;Communications in Computer and Information Science;2014

5. SCIN-cache;ACM Transactions on Architecture and Code Optimization;2013-01

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