Author:
Pircher S.,Geier J.,Zeh A.,Mueller-Gritschneder D.
Cited by
8 articles.
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1. Optimised AES with RISC-V Vector Extensions;2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS);2024-04-03
2. A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator;Lecture Notes in Computer Science;2024
3. RISC-V for Genome Data Analysis: Opportunities and Challenges;2023 38th Conference on Design of Circuits and Integrated Systems (DCIS);2023-11-15
4. Punctured Syndrome Decoding Problem;Constructive Side-Channel Analysis and Secure Design;2023
5. Efficient Support of the Scan Vector Model for RISC-V Vector Extension;Workshop Proceedings of the 51st International Conference on Parallel Processing;2022-08-29