Power-Area Efficient Computing Technique for Approximate Multiplier with Carry Prediction
Author:
Affiliation:
1. Shri Ramdeobaba College of Engineering and Management,Department of Electronics Engineering,Nagpur,India
2. Shri Ramdeobaba College of Engineering and Management,Department of Electronics and Communication Engineering,Nagpur,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10150431/10151452/10151588.pdf?arnumber=10151588
Reference15 articles.
1. Design and Analysis of Multiplier Using Approximate 15-4 Compressor;marimuthu;IEEE Access,2016
2. Low-power high-speed multiplier for error-tolerant application;kyaw;EDSSC,2010
3. A low-power, high-performance approximate multiplier with configurable partial error recovery;liu;Proc Conf Exhibit (DATE),2014
4. Design of Power and Area Efficient Approximate Multipliers
5. Implementation of High Performance Multipliers Based on Approximate Compressor Design;ma;international Conference on Electrical and Control Technologies (ECT),2011
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1. Two energy efficient unsigned approximate multipliers with N-4 compressors;IEICE Electronics Express;2024-07-25
2. Design and Implementation of High-Performance Multi-Level Approximate Multiplier;2024 International Conference on Distributed Computing and Optimization Techniques (ICDCOT);2024-03-15
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