Author:
Kagalkar Aishwarya,Raghuram S.
Cited by
20 articles.
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1. Exploring Hardware Activation Function Design: CORDIC Architecture in Diverse Floating Formats;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03
2. Low-Complexity lassification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06
3. EBACA: Efficient Bfloat16-based Activation Function Implementation Using Enhanced CORDIC Architecture;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06
4. An Energy-Efficient Architecture of Approximate Softmax Functions for Transformer in Edge Computing;2023 6th International Conference on Electronics and Electrical Engineering Technology (EEET);2023-12-01
5. Activation Function Conundrums in the Modern Machine Learning Paradigm;2023 International Conference on Computer and Applications (ICCA);2023-11-28