Fault Tolerant FPGAs: Where to Spend the Effort?
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8867828/8875008/08875164.pdf?arnumber=8875164
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. MTTR reduction of FPGA scrubbing: Exploring SEU sensitivity;Microprocessors and Microsystems;2023-09
2. The Approach to Assessment of Technical Condition of Microprocessor Systems that Are Implemented on Integrated Circuits with a Programmable Structure;Emerging Networking in the Digital Transformation Age;2023
3. A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs;2020 30th International Conference on Field-Programmable Logic and Applications (FPL);2020-08
4. LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs;2020 30th International Conference on Field-Programmable Logic and Applications (FPL);2020-08
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